Linearity Improvement of Cascode Cmos Lna Using a Diode Connected Nmos Transistor with a Parallel Rc Circuit

A fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) using post-linearization technique, implemented in a 0.18μm RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise figure (NF) and power consumption. The LNA achieves an input third-order intercept point (IIP3) of +8.33 dBm, a power gain of 10.02 dB, and a NF of 3.05 dB at 5.5GHz biased at 6 mA from a 1.8V power supply.